The invention pertains to an MOS memory device. More specifically, the invention pertains to a static-type MOS RAM (Random Access Memory) which has a non-volatile back-up storage capability.
A great deal of research activity has recently been conducted to develop a non-volatile random access memory on a single silicon chip. Prior to the availability of non-volatile random access memories fabricated on a single silicon chip, the most common way of achieving non-volatility was to provide a battery back-up for the MOS memory. When a main power supply failed, the battery was automatically switched in to power the device until the main power source could be brought back on-line. This arrangement was generally not satisfactory because the battery was expensive, the battery required periodic maintenance and replacement and, if the battery failed, the data stored in the memory was disastrously lost. For these reasons, it is desirable to provide a non-volatile random access memory which does not require a battery back-up.
A non-volatile memory device fabricated on a single silicon chip is disclosed in "Dual-Electron Injector-Structure Electrically Alterable Read-Only Memory Model Studies", DiMaria et al., IEEE Transactions on Electron Devices, Vol. ED-28, No. 9, September 1981, and in co-pending patent application Ser. No. 124,003, filed Feb. 26, 1980, which is assigned in common with the present application. This memory device uses a cell structure composed of an n-channel MOS transistor with DEIS (Dual Electron Injector Stack) material positioned between a control gate and a "floating" polycrystalline silicon gate. Writing is performed by applying a negative voltage to the control gate. This negative voltage causes the injection of electrons from the top silicon-rich SiO.sub.2 injector layer of the DEIS material to the floating polysilicon layer. Similarly, erasing is performed by applying a positive voltage to the control gate, which then injects electrons from a bottom silicon-rich SiO.sub.2 injector layer of the DEIS material to the floating polysilicon layer.
The DEIS material is formed by a layer of insulating SiO.sub.2 sandwiched between two silicon-rich SiO.sub.2 injector layers. Polysilicon layers are located immediately outside the silicon-rich SiO.sub.2 injector layers, the lower one of which forms the floating gate electrode and the upper one of which is connected to a gate line.
While this memory device does in fact provide non-volatile storage capability and is quite useful in a number of applications, it is still not acceptable for many applications in which random access memories have customarily been employed. The reasons for this are that the relatively long reading and writing times are required to get data in and out of the memory cells. Moreover, there is a serious drawback in that only a limited number (for instance, 10,000) reading and writing operations can be performed in a cell of this type.
To achieve higher normal operating speeds while retaining a non-volatile memory capability, several proposals have been made to pair non-volatile back-up storage cells with faster storage cells which do not have the non-volatile storage capability. During normal continuous operations, the memory operates using the volatile cells. If the power supply fails, back-up power is supplied for a relatively short period of time from a storage source such as a capacitor bank. As soon as the main power supply fails, data from the volatile cells is transferred to their paired non-volatile cells using the power from the back-up power source. When the normal power source is back on-line, a data transfer operation is made from the non-volatile cells back to the volatile cells, and then normal memory operation is continued. Examples of memories of this type using a static RAM configuration are described in "Five-Volt-Only, Non-Volatile RAM Owes It All To Polysilicon", Electronics, Oct. 11, 1979, pp. 111-116; "Completely Electrically Erasible Memory Behaves Like A Fast, Non-Volatile RAM", Electronics, May 10, 1979, p. 128; Drori et al., "A Single 5 V Supply Nonvolatile Static RAM", 1981 IEEE International Solid State Circuits Conf. Proc., Feb. 19, 1981 pp. 148, 149; Kotecha et al., "A Dual-Gate Floating-Gate FET Device", 1981 IEEE International Solid State Circuits Conf. Proc., Feb. 18, 1981 pp. 38, 39; U.S. Pat. No. 3,676,717, issued July 11, 1972 to Lockwood; and co-pending U.S. Pat. applications Ser. Nos. 192,579 now U.S. Pat. No. 4,388,704 and 192,580 now U.S. Pat. No. 4,399,522, filed Sept. 30, 1980 and assigned in common herewith.
Although the devices of these proposals do in some cases provide an increased minimum operating speed together with non-volatile storage for use during times of power failure, the density of the memory cells is not attractive on a cost/performance basis compared to a battery powered volatile random access memory arrangement.
The undesirably large cell required, for instance, in the memory described in "Five Volt Only Non-Volatile RAM Owes It All To Polysilicon", supra. is due to the relatively large breakdown voltages at the diffusion-to-substrate junction of the device which must be accommodated. Specifically, the maximum allowable voltage that can be applied to an N.sup.+ diffusion is determined by the breakdown voltage BV.sub.N-P of an N.sup.+ P junction, which may be written as: EQU BV.sub.N-P =MV.sub.G +BV.sub.GO
where V.sub.G is the gate voltage of the device, M is a constant close to unity and BV.sub.GO is the zero gate breakdown voltage.
When a device is scaled down to achieve a desired cell size, the doping levels of the various diffusions and the junction depths are scaled. This results in a reduction of the term BV.sub.GO, and hence a decrease in the breakdown voltage.
Another drawback of prior art approaches, for instance, that of the Lockwood patent, is that, when a restore operation is performed when power is applied to the device to transfer data from non-volatile to volatile storage, the data in the non-volatile storage elements is lost. Hence, such memories have no latent image capability; that is, they cannot retain data in the non-volatile storage elements following a restore operation.
Another reason that prior art approaches have failed to achieve a desirably small cell size relates to the way in which the various capacitances within a memory cell are fabricated. For example, in the memory cell of the above-mentioned article "A Floating Gate FET Device", a relatively thick oxide layer lying between two levels of polysilicon conductors is used to form the dielectric material of the cell capacitors. Because of this, the size of the capacitors is larger than is desirable.
Thus, it is a primary object of the present invention to provide a high speed RAM device having a non-volatile back-up storage capability.
Further, it is an object of the present invention to provide such a memory device in which, in addition to the non-volatile storage capability, a latent storage capability is also provided.
It is yet a further object of the present invention to provide such a memory device having a very small cell size and simple construction.
It is also an object of the present invention to provide a method of operating such a memory device.